At present, in a circuit structure of the shift register unit, an output end of the shift register unit and a pull-up node are reset simultaneously by utilizing a special output reset transistor and a special node reset transistor. As shown in FIG. 1, gates of an output reset transistor T4 and a node reset transistor T2 of the shift register unit are connected with a reset input end, and the output end and the pull-up node are reset respectively under control of a reset signal input by a reset input end. In order to reduce reset time of the shift register unit, it requires enlarging an area of the output reset transistor T4, such that a turn-on voltage of the output reset transistor T4 is relatively small. However, it is apparent that enlarging the area of the reset transistor T4 is obviously not helpful to enhance resolution of a display device and narrow frame of the display device.
There has been set forth a solution of resetting the output end and the pull-up node of the shift register unit in a time division manner. As shown in FIG. 3, compared with FIG. 1, the output reset transistor T4 is no longer comprised, the gate of the node reset transistor T2 receives the reset signal, and when a clock signal CLK is switched from a high level to a low level, the pull-up node is at the high level, an output transistor T3 maintains turned on and resets the output end to low level of the clock signal CLK. Although the output reset transistor T4 is omitted in FIG. 3, the shift register unit as shown in FIG. 3 still cannot satisfy the requirement for products as the resolution of the display is further enhanced and the requirement for the narrow frame is further enhanced.
Therefore, it needs to propose a shift register unit, which is capable of not only reducing the area of the shift register unit but also reducing the reset time of the output end of the shift register unit.